"Evolution of VLSI Industry, Detailed Understanding of VLSI Design Flow, ASIC and its requirements , Understanding FPGA , ASIC vs FPGA, VLSI technology terms, Standard IEEE specifications, Protocols and Bus Standards are discussed in detail Detailed Understanding of System Verilog, Verification techniques, RTL Verification, Gate Level Verification, Post Silicon Verification, OVM, UVM."
He is an IEEE member. He got 2 US Patents and several research papers published in reputed journals. He is the winner of IBM Outstanding Technical Achievement Award (OTAA) .
He got expertise in SoC Chip design with multi-million gates .
He is a VLSI hardware architect & working as a consultant for various VLSI companies.
- Focused Training with Practical aspects of VLSI design
- Designed with a mix of Experience, Real time designs, Case-Studies, Assignments besides class lectures
- VLSI Industry, including Hardware, Software,Firmware Layers are covered
- On Completion of this Program, students will be able to understand VLSI design flow, VLSI & Embedded Industry Trends and Job opportunities in India
- Designed for Engineering College Students & Faculty of below stream
- Computer Science
- ME VLSI Design / Embedded
- VLSI Professionals
- Evolution of VLSI Industry
- VLSI Design Flow
- Understanding ASIC, FPGA
- System on Chip (SoC)
- Hardware Description Languages : VHDL, Verilog HDL
- Front End Design using Verilog
3. RTL (Register Transfer Level)
- RTL Design using Verilog
- Important Features of Verilog for Front End Design.
- Memory Protocols – DDR3
- IEEE Standards, Bus Protocols
- USB, PCIx, ARM, AXI, AHB, APB, OCP etc.
- Current Trends in VLSI industry in India
- Job Trends & Opportunities
- FLIP FLOP / LATCHES
- ADDERs , MULTIPLIERS
- Pattern Detector
- Workshop Certificate
- Certificate for completion of mini project during the workshop.
Duration:2 day; 8 hours/day;
Topics CoveredModule-1 : VLSI Front End Design- ASIC, SOC & SDRAM Design Process
1. VLSI Design Flow
2. Importance of Verification in VLSI chip Design
3. Different Verification Techniques
1. Simulation Based
2. Emulation & Validation Platform Based
3. Formal & Assertions Based
4. Different Stages of Chip Verification
- RTL Verification
- Gate Level Verification
- Post Silicon Verification
5. Verification using System Verilog
- Evolution of System Verilog
- Verilog vs System Verilog
- System Verilog for Verification
- Important System Verilog Features
- Design Examples and Verification Environment using System Verilog
6. Introduction to Latest Verification Methodologies
7. Role of EDA tools in Chip Verification
8. Latest , Advanced & Futuristic Trends in VLSI Verification
9. Industry Overview & Job Opportunities in VLSI Verification in India.
Module-3 :Below VLSI Blocks discussed in detail and will be implemented and verified:
Each participant will get two certificates:
A competition will be organized at the end of the workshop. Winners of this competition will get "Certificate of Excellence".