Advanced level workshop on  System Verilog & Verification Techniques

Advanced level workshop on System Verilog & Verification Techniques

 

  • Seat Confirmation Fees - Rs.1000

    Pay Rs.1000 as seat confirmation fees, remaining amount will have to be paid on the day of workshop.

    Sale Date Ended

    INR 1000
    Sold Out

Invite friends

Contact Us

Page Views : 273

About The Event

Introduction:

"Evolution of VLSI Industry, Detailed Understanding of System Verilog, Verification techniques, RTL Verification, Gate Level Verification, Post Silicon Verification, OVM, UVM." 

Trainer's Profile

Mr. Ravi Lakshmipathy  is a veteran in VLSI field. He has 15+ years of experience in VLSI. He held senior positions in  Texas Instruments  &  IBM . He is MS in Micro-electronics from  BITS, Pilani .
He is an IEEE member. He got  2 US Patents  and several research papers published in reputed journals. He is the winner of  IBM Outstanding Technical Achievement Award (OTAA) .
He got expertise in  SoC Chip design with multi-million gates .
He is a VLSI hardware architect & working as a consultant for various VLSI companies.

 

Uniue features:

  • Focused Training with Practical aspects of VLSI design
  • Designed with a mix of Experience, Real time designs, Case-Studies, Assignments besides class lectures
  • VLSI Industry, including Hardware, Software,Firmware Layers are covered
  • On Completion of this Program, students will be able to understand VLSI design flow, VLSI & Embedded Industry Trends and Job opportunities in India
  • Target Audience

    • Designed for Engineering College Students & Faculty of below stream
      • ECE
      • EEE
      • Computer Science
      • ME VLSI Design / Embedded
    • VLSI Professionals

    Duration:

    1 day; 8 hours/day;

    Content:

    Topics Covered

    1. VLSI Design Flow
    2. Importance of Verification in VLSI chip Design
    3. Different Verification Techniques
    1. Simulation Based
    2. Emulation & Validation Platform Based
    3. Formal & Assertions Based
    4. Different Stages of Chip Verification
    - RTL Verification
    - Gate Level Verification
    - Post Silicon Verification
    5. Verification using System Verilog
    - Evolution of System Verilog
    - Verilog vs System Verilog
    - System Verilog for Verification
    - Important System Verilog Features
    - Design Examples and Verification Environment using System Verilog
    6. Introduction to Latest Verification Methodologies
    1. OVM
    2. UVM
    7. Role of EDA tools in Chip Verification
    8. Latest , Advanced & Futuristic Trends in VLSI Verification
    9. Industry Overview & Job Opportunities in VLSI Verification in India.

    Below VLSI Blocks discussed in detail and will be verified using various verification techniques:

    1. FLIP FLOP / LATCHES
    2. MUX
    3. FIFO
    4. ADDERs , MULTIPLIERS
    5. MEMORY
    6. FIFO
    7. Pattern Detector

    Certification:

    Each participant will get two certificates:

    1. Workshop Certificate
    2. Certificate for completion of mini project during the workshop.

    A competition will be organized at the end of the workshop. Winners of this competition will get "Certificate of Excellence".

Fees Structure:

Fees For Professionals:   2000/-(inclusive of all taxes & tutorial+software DVD)
Fees For Faculties from colleges & other educational institutes(ID card compulsory):   1500/-(inclusive of all taxes & tutorial+software DVD)
Fees For Students from colleges & other educational institutes(ID card compulsory):
  1. Fees for the team of 2 persons : 1500/-(inclusive of all taxes & tutorial+software DVD)
  2. Fees for the team of 1 person : 1,000/-(inclusive of all taxes & tutorial+software DVD)

Totorial + Software DVD contents:

 You will get a DVD with Tutorials & Software tools at the end of the workshop.

Venue:

@Chennai:
Tech Innovates Lab, No.80, III Floor, V.V. Koil Street, Anna Nagar West Extension, Chennai-40. Land mark - Near Thirumangalam Signal.

Venue Map