Workshop on VLSI Front End Design- ASIC, SOC and SDRAM Design Process

Workshop on VLSI Front End Design- ASIC, SOC and SDRAM Design Process

 

  • Seat Confirmation fees- Rs.1000

    Seat Confirmation fees- Rs.1000

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About The Event

"Evolution of VLSI Industry, Detailed Understanding of VLSI Design Flow, ASIC and its requirements , Understanding FPGA , ASIC vs FPGA, VLSI technology terms, Standard IEEE specifications, Protocols and Bus Standards are discussed in detail"

Trainer's Profile
Mr. Ravi Lakshmipathy  is a veteran in VLSI field. He has 15+ years of experience in VLSI. He held senior positions in  Texas Instruments  &  IBM . He is MS in Micro-electronics from  BITS, Pilani.

  1. He is an IEEE member. He got  2 US Patents  and several research papers published in reputed journals. He is the winner of  IBM Outstanding Technical Achievement Award (OTAA).
  2. He got expertise in  SoC Chip design with multi-million gates .
  3. He is a VLSI hardware architect & working as a consultant for various VLSI companies.


Uniue features:

  1. Focused Training with Practical aspects of VLSI design
  2. Designed with a mix of Experience, Real time designs, Case-Studies, Assignments besides class lectures
  3. VLSI Industry, including Hardware, Software,Firmware Layers are covered
  4. On Completion of this Program, students will be able to understand VLSI design flow, VLSI & Embedded Industry Trends and Job opportunities in India



Target Audience

  1. Designed for Engineering College Students & Faculty of below stream
  2. ECE
  3. EEE
  4. Computer Science

 

ME VLSI Design / Embedded
VLSI Professionals
    Duration:
    1 day; 8 hours/day;
    Content:

 

Topics Covered

  1. Evolution of VLSI Industry
  2. VLSI Design Flow
  3. Understanding ASIC, FPGA
  4. System on Chip (SoC)
  5. Hardware Description Languages : VHDL, Verilog HDL
  6. Front End Design using Verilog Structural, Behavioural, RTL (Register Transfer Level)
  7. RTL Design using Verilog
  8. Important Features of Verilog for Front End Design.
  9. Memory Protocols – DDR3
  10. IEEE Standards, Bus Protocols
  11. USB, PCIx, ARM, AXI, AHB, APB, OCP etc.
  12. Current Trends in VLSI industry in India
  13. Job Trends & Opportunities
  14. Conclusion

Below VLSI Blocks discussed in detail and will be implemented:

  1. FLIP FLOP / LATCHES
  2. MUX
  3. FIFO
  4. ADDERs , MULTIPLIERs
  5. MEMORY
  6. FIFO
  7. Pattern Detector   

Certification:

Each participant will get two certificates:

  1. Workshop Certificate
  2. Certificate for completion of mini project during the workshop.


 A competition will be organized at the end of the workshop. Winners of this competition will get "Certificate of Excellence".

Fees Structure:
Fees For Professionals:   2000/-(inclusive of all taxes & tutorial+software DVD)
Fees For Faculties from colleges & other educational institutes(ID card compulsory):   1500/-(inclusive of all taxes & tutorial+software DVD)
Fees For Students from colleges & other educational institutes(ID card compulsory):

    Fees for the team of 2 persons : 1500/-(inclusive of all taxes & tutorial+software DVD)
    Fees for the team of 1 person : 1,000/-(inclusive of all taxes & tutorial+software DVD)

Totorial + Software DVD contents:
 You will get a DVD with Tutorials & Software tools at the end of the workshop.
Venue:

@Chennai:
Tech Innovates Lab, No.80, III Floor, V.V. Koil Street, Anna Nagar West Extension, Chennai-40. Land mark - Near Thirumangalam Signal.

Venue Map